1. Field of the Invention
The present invention relates to a circuit simulator and, more particularly, it relates to a circuit simulator for simulating operation of an electronic circuit while finding a timing error caused in respective elements thereof.
2. Description of the Background Art
In a logic circuit design, a circuit simulator is widely used as a means for verifying its logic operation and timing. Also, there exists a simulator dedicated only to the verification of operation timing.
FIG. 1 is a flowchart showing conventional process for a timing verification which is conducted in the circuit simulator.
At step S1, the circuit simulator generates an electronic state equivalently representing the condition where input test pattern signals are applied to input terminals of an object circuit to be simulated, and then calculates output signals of respective elements on the basis of operation characters and input waveforms thereof, whereby the circuit is simulated.
At step S2, it is tried to detect a timing error in input and output signals of respective elements with reference to the simulation result in Step S1.
If a timing error is detected at Step S3, the process proceeds to Step S4. At Step S4, outputted is an error message list including information as to the kind of a timing error, the time when the error was caused, the element in which the error was caused, which is useful to investigate the cause of a timing error. Meanwhile, no timing error is found at Step S3, the process proceeds to Step S5. At Step S5, it is checked whether the simulation for all the elements in the object circuit is completed. If the simulation has not been completed for one or more elements, the process returns to Step 1. Thus, Steps S1 to S5 are repeated until the simulation is completed for all the elements.
Since the conventional timing error message which is outputted from the conventional circuit simulator of includes information only as to the kind of a timing error, the time when the error was caused, the element in which the error has been caused, an operator is obliged to spend considerable time to investigate the cause of the timing error.